1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device using CMP (Chemical mechanical Polishing).
2. Description of the Related Art
Conventionally, in a semiconductor device having a damascene structure, wirings and vias are formed using the Chemical Mechanical Polishing.
Typical wiring forming process in a method of fabricating a semiconductor device having the damascene structure is hereinafter described.
First, as shown in FIG. 1a, grooves 102 are formed in portions of oxide film layer 101 where wirings are to be formed.
Next, as shown in FIG. 1b, barrier layer 103 made of tantalum is deposited on the entire surface of oxide film layer 101 including grooves 102 formed therein.
Then, as shown in FIG. 1c, conductive layer 104 made of Cu is deposited on the entire surface of barrier layer 103. The Cu is thus embedded in grooves 102.
Next, conductive layer 104 is polished by performing primary polishing using the CMP to expose barrier layer 103 except for its portions on grooves 102. Thus, as shown in FIG. 1d, wirings 105 are formed in the portions where grooves 102 are formed.
Secondary polishing using the CMP is then performed to remove barrier layer 103 except for the portions on grooves 102 as shown in FIG. 1e. 
With the aforementioned series of steps, wirings 105 for the semiconductor device are formed.
Next, the polishing process using the CMP of the aforementioned steps are described in detail with reference to FIG. 2.
As shown in FIG. 2, support member 20 on which wafer 21 is mounted is brought into close contact with surface plate 10 having an upper surface on which urethane pad 12 is mounted such that urethane pad 12 is in contact with wafer 21. In this state, surface plate 10 is rotated while slurry 30 containing free abrasives is supplied onto urethane pad 12. In this manner, a surface of wafer 21 is polished. At this point, support member 20 also is rotated about the axis.
Typically, slurry containing alumina is used in the primary polishing in FIG. 1d. Slurry containing silica is used in the secondary polishing in FIG. 1e. This is because alumina provides a higher polishing speed than silica and is advantageous in removing Cu, while silica presents less occurrence of scratches on the wafer surface than alumina and is advantageous in removing tantalum.
Japanese Patent Laid-open Publication No.1998-296610 discloses a polishing method in which a fixed abrasive pad including abrasives embedded therein is used in stead of urethane pad 12 shown in FIG. 2 and a wafer surface is polished while slurry containing free abrasives is supplied onto the fixed abrasive pad. The amount of the abrasives contained in the slurry supplied onto the fixed abrasive pad is equal to or higher than 1% by weight.
The polishing method can realize high flatness of the wafer due to the use of the fixed abrasive pad. In addition, the supply of the slurry containing the abrasives can provide a higher polishing speed.
However, in a method of fabricating a semiconductor device using the polishing process as shown in FIG. 2, since the wafer surface is polished by the slurry supplied between the urethane pad and the wafer in the polishing steps, the abrasives in the slurry produce concave portions in the wafer surface, and the abrasives are introduced into the concave portions to further dig the concave portions.
As shown in FIG. 3, abrasives 31 in the slurry supplied between urethane pad 12 and wafer 21 are introduced into the concave portions produced in the surface of wafer 21 to further dig the concave portions. Since urethane pad 12 is made of a soft material, deformation occurs in portions of urethane pad 12 where many abrasives 31 in the slurry are introduced to cause more of the abrasives to be introduced into the concave portions in the surface of wafer 21, resulting in further digging of the concave portions.
In the secondary polishing step thereafter, the concave portions produced in the surface of wafer 21 in the primary polishing step are further dug similarly to the aforementioned manner.
Such digging leads to a problem that dishing or erosion produced on the wafer surface is increased to vary wiring resistance.
On the other hand, in the polishing method disclosed in Japanese Patent Laid-open Publication No.1998-296610, since the slurry containing the abrasives is supplied onto the fixed abrasive pad, the abrasives are introduced into concave portions produced in the wafer surface to further dig the concave portions, causing a problem similar to the aforementioned problem.
It is an object of the present invention to provide a method of fabricating a semiconductor device capable of suppressing variations in wiring resistance caused by dishing and erosion.
First, in a primary polishing step, a substrate is brought into close contact with a first pad including abrasives and made of a hard material, and the first pad is rotated while a first solution containing no abrasive is supplied onto the first pad to polish a surface of the substrate. In the primary polishing step, since the first solution contains no abrasive and the first pad is hard, polishing is performed with high flatness and extremely less dishing and erosion. However, many scratches occur on the polished surface of the substrate since the first solution contains no abrasive and the first pad includes the abrasives and is hard. Thus, in a secondary polishing step, the substrate is brought into close contact with a second pad including no abrasive and made of a soft material, and the second pad is rotated while a second solution containing abrasives is supplied onto the second pad to polish the surface of the substrate. In the secondary polishing step, the scratches produced in the primary polishing step are reduced since the second solution contains the abrasives and the second pad is soft.
With this method, the scratches produced on the substrate surface are reduced and the dishing or erosion produced on the substrate surface is suppressed to improve the flatness of the substrate surface.
When a substrate is brought into close contact with a pad including abrasives and the pad is rotated while a solution containing an abrasive whose content is 0.8% by weight or lower is supplied onto the pad to polish a surface of the substrate, the amount of the abrasives are introduced into concave portions in the substrate surface is reduced since the contained amount of the abrasives in the solution is 0.8% by weight or lower, thereby suppressing further digging of the concave portions.
The above and other object, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.